SemiSerious

Leaving things until the last minute is certainly nothing new for me, but I might be better off waiting to summarize next week’s IEDM than trying to preview it here. These days, there is a constant flow of negative news in the chip industry and the wider economy, so thinking about the research and development side of things for a while is a welcome break. Those actually at the conference may not have the luxury of avoiding the recessionary indicators since widespread cost-cutting is sure to make the event much smaller than usual. At least moving around at the coffee breaks will be easier.

Back to the concept of the preview, I had the really good fortune to speak directly to both IBM and Intel about their upcoming papers. Mark Bohr promoted presentations from three different technology angles that will appear at IEDM this year. The highlight is certainly the late news paper that Sanjay Natarajan will present. Sanjay is the Manager of Intel’s 32nm CMOS Technology Development and will provide a little more information on what is coming from their second generation HKMG. The emphasis will be on “little.” Intel rarely discloses much about their processes, but they have already released a couple of key metrics:

World’s tightest gate pitch of 112.5nm, and
World’s best drive currents - 1.55µA/µm for NFET’s and 1.21µA/µm for PFET’s.

You may see a pattern here. Intel likes to be way out front when it comes to numbers like this, and they certainly plan and make the investments necessary to achieve and maintain their lead. Last year at the Intel Developer Forum, Sanjay noted that the release of their first 32nm SRAM test chip was only 20 months after the 45nm version - well ahead of Intel’s already aggressive two year cadence for technology node introduction. Based on the combination of their process technology, transistor performance and timing production ramps for these nodes, Mark Bohr believes that Intel is “more than one generation ahead of the rest of the industry.” But even if they won’t reveal details of their 32nm process, Intel never needs to say much to draw a crowd. Whatever it is will be big news at this conference. Intel + 32nm is bound to have everyone buzzing.

The second paper Mark Bohr presented to analysts is about enhancing Intel 45nm for low power and SoC applications. Of course, HKMG can give you very powerful transistors, but it can also give acceptable levels of drive while keeping power consumption way down. Chia-Hong Jan’s 45nm SoC paper will claim that the low power process achieves less than 1nA/µm leakage. That’s bound to help battery life as well as Intel’s push to gain a bigger piece of the hand-held computing market. Atom-based based netbooks are surely not the end game in Intel’s aspirations of becoming more accepted into more mobile and portable platforms. The SoC process includes finger capacitors and high Q inductor elements. I wonder what they will build with this technology. It’s worth a trip to the Intel job board to see what kind of analog and RF people they might be looking for.

The third paper touted by Intel PR for the upcoming IEDM takes a longer view. Marko Radosavljevic’s paper on InSb transistors takes a much longer view of the technology roadmap than the previous two entries. Marko’s talk will build on previous work that disclosed n-channel devices with the IEDM paper in p-channel InSb quantum well transistors. Although they have not integrated the two yet, the goal of this work is to create a complete complimentary logic platform to replace silicon in the 2015 time frame. Intel really takes the very long term view of maintaining Moore’s Law. It’s not just the next few ticks of the tick-tock strategy that keeps them busy. Of course, Intel also does a lot of work with exotic silicon devices like FinFET’s as well, but the new channel materials may end up actually requiring fewer changes to the approach to design and manufacturing of IC’s simply by sticking to a planar technology.

Speaking of upcoming ticks though, IBM is very excited about both its 32nm bulk foundry process and its progress towards a viable 22nm technology. Dr. An Steegen will present a paper outlining key features of IBM’s 32nm bulk process. It will be offered in two versions. The first to ramp will be a low power version. IBM will introduce a high-k metal gate stack for the first time at 32nm. Migrating to HKMG from conventional poly gates with SiON dielectrics offers a very low leakage option. This flavor will not employ any strain engineering to enhance carrier mobility. However, the high performance version adds all the well-known stress elements to increase FET drive current. IBM doesn’t pre-release those numbers, so get to the conference or check back here. Better yet, take a look over at EETimes because Mark LaPedus will be keeping the broader community well informed of all the key developments at IEDM as they occur. Dr. Steegen and her team are rightfully proud of their accomplishment in 32nm. They like to point out that their gate first approach to HKMG allows the freedom of conventional gate layout without the need for restricted design rules required by the replacement gate flow used by Intel.

The IBM team at Albany Nanotech is pumped up about their recent progress toward 22nm. Dr. Bruce Doris believes that the rest of the industry should be too. The team will discuss their world record 22nm SRAM that boasts a cell size less than a tenth of a square micron. Proving that an SRAM cell works at the 22nm built on standard 300mm tools is great news for the whole industry and will ease concerns over extending this conventional memory to future nodes. The IBM 22nm SRAM certainly proves the viability of conventional planar CMOS for the next few years, so neither design nor manufacturing flows need to be turned onto their heads by FinFETs or some other exotic device.

In the technology race between Intel and competitors like IBM and AMD, it often seems to boil down to a choice about what to keep. For Intel at 45nm, they kept dry litho but gave up on conventional layout and moved to a restricted set of design rules with regular parallel patterns to give their existing dry litho tools a chance to keep doing the job. On the other hand, IBM and its technology partners like AMD opted to invest in immersion lithography earlier which allowed them to stick with conventional polysilicon layout rules. But there is not avoiding either of these approaches. Intel is using immersion lithography at 32nm. IBM has talked about restricted design rules and computational lithography to get to 22nm and beyond. That makes it hard to pick the best technology. Or it makes it harder for an analyst to be wrong. Either way, I don’t plan to stick my neck out. My colleagues Ramesh Kuchibhatla and Dr. Vu Ho will be at the conference. Talk to one of them. Both are seasoned technology veterans and not shy about giving you their opinion.

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I’m not suggesting any cause and effect, but three weeks after trading in my gas guzzling minivan for an economy car rated at 6.2 litres per 100km, gas prices here in Ottawa are set to dip below $0.80 per litre. (Actually, it’s taken a week to get around to finishing this post, and I actually filled up at $0.795 over the weekend.) That’s territory that’s been unknown to the Canadian national capital region’s drivers since the early days of 2007. The EIA also reported that the average US retail price for gasoline dropped below US$2.40 per gallon for the first time since early 2007.

It seems that even experts in this field are not able to explain the connection between gas prices at the pump and world prices for oil, but there must be some loose correlation, maybe with a random phase term thrown in. Anyway, the gas price we are currently enjoying encouraged me to take a look at oil which appears set to drop below US$60 per barrel, a price that has not been seen since March of 2007.

So what has oil got to do with semiconductors? And no, this is not another article about Abu Dhabi buying AMD’s fabs. Global warming is a big concern and a hot button topic without a doubt. Biking to work in shorts in November is one data point supporting the theory that we are heating up. (Last winter in Ottawa, though, was an entirely different story.) It’s not just the concerns over greenhouse gas emissions and their effect on climate change that’s driving renewable energy sources like solar power though. Government policy everywhere from China to Europe has been shaped by oil price shocks in the past and the oft-referred to age of “peak oil” that is reportedly upon us. But with petroleum prices now falling, many have begun to wonder how interesting photovoltaics and other renewable energy sources will be, at least to investors.

There is no doubt that rising oil prices in the 1970’s kick-started research into photovoltaics. This is seen in the chart below that tracks world oil price (yearly average) against the number of patent applications submitted to the USPTO. With oil now dropping, what will happen to the investment in photovoltaics?

Fortunately, there is some earlier history of oil price relaxation to draw on for an answer. Going back to the eighties, oil dipped from a high of $34 in 1983 to around $13 in 1989. But interest in photovoltaics - at least as measured by patent activity - did not decline. In fact, patent applications continued to increase despite the drop in oil price. But why? It appears related to government policy as the US Congress extended legislation from the seventies to continue investment into various forms of renewables. Bill Clinton and Al Gore also wasted little time pushing renewable energy at the DOE with their appointments to that body in 1993.

The first big oil price shocks may have spawned the renewable energy industry, but what was happening around 2000 when USPTO applications began to take a nosedive? Backlogs at the patent office put a negative bias on the data, so it often appears that activity is slowing drastically as the graph approaches today’s date. Once applications in the queue finally get published, the sharp drop in patents softens or disappears. Unfortunately for analysts like me, you need to travel into the future to get that accurate data. To be on the safe side, I cut this graph off after 2005. But there’s still a dramatic decline in activity between 2000 and 2005. Why?

At a time when interest in photovoltaics appeared to be waning, oil was simmering in preparation for the insane rise in price that reached a peak of nearly $140. And now, the price has been spiralling down with the rest of the world economic indicators. Where does that leave photovoltaics?

I think the bottom line is that the idea of dependence on unpredictable, uncontrollable foreign oil and maybe even the notion that the end of the world supply might be in sight has prompted the governments of several powerful countries to enact strategic programs that have established a solid future for photovoltaic development independent of a high spot price for oil. I don’t think that even the most ardent supporter of the green movement would claim that any present-day renewable energy technology could displace traditional power plant fuels competing head-to-head on an equal economic footing. It takes time to transition, so here is one place where governments have an important role to play in ensuring that photovoltaics and other renewable energy sources are ready to meet the demand when we no longer have an option.

But there are certainly fears that the feed-in tariffs and other subsidies that have kept the solar ball rolling could be under pressure. These days, there’s lots of bad economic news and speculation of even more fear and uncertainty around the corner. Faced with the difficult times and relatively short political terms of office, governments will find it harder to continue a longer term strategic view when it comes to energy. If things get as bad as some are predicting, even a newly elected visionary US president may have to postpone spending on renewable energy.

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Toshiba is the first flash manufacturer to incorporate a high-K dielectric in their product. Their innovative inter-poly dielectric has allowed Toshiba to scale their floating gate flash memory to 43nm. The 16Gbit multi-level cell (MLC) device from Toshiba sets the new high watermark for NAND flash bit density at 139Mbits/mm².

Samsung claimed the first implementation of high-K dielectric for flash. However, that was for a charge-trapping (CTF) device they expected to roll out for 4Xnm. By now, we have all heard a lot about TANOS flash from Samsung. There is no floating gate with CTF, so the high-K material is in the tunnel oxide between the silicon channel and the control gate of the memory cell. The TANOS concept first announced by Samsung at IEDM 2005 was an extension to the generic SONOS approach of an oxide/nitride/oxide sandwich for charge trapping much like the so-called O-N-O inter-poly dielectric routinely used to separate the control and floating gate in traditional flash devices. The SONOS acronym was derived from the silicon on top (poly gate) of the dielectric and the silicon substrate underneath. SANOS CTF devices increased the dielectric constant of the charge trapping dielectric to allow the layers to electrically scale without sacrificing reliability by physically thinning the layers. The ‘A’ in SANOS comes from the aluminum-oxide high-K material. The last step to get to TANOS was for Samsung to substitute a tantalum-nitride metal gate in their CTF.

The bottom line from that wordy, acronym-laden paragraph is that floating gate was supposedly running out of steam and CTF devices were going to replace them. That’s what generated all the buzz and all the lovely new acronyms. Despite many “expert” predictions over the years, reports of the death of floating gate flash are greatly exaggerated. On the contrary, floating gate technology continues to dominate the market. I wonder if the floating gate technologists at Toshiba are having a good laugh because they were first to market with high-K which was a big part of the CTF that was supposed to put them out of business.

Many more details on this innovative flash process from Toshiba are available from Semiconductor Insights.

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Our marketing team recently launched the latest instance of the popular Insight Awards Program. We are rabidly seeking your submissions to the contest. This year, it is a coordinated event between EE Times, Portelligent, and Semiconductor Insights.

If you haven’t heard about this program before, it is a chance to use us to showcase your technology. But first, you need to submit your samples. Then Semiconductor Insights’ and Portelligent’s crack teams of technology analysts will compare your device to your competition. We pick the winner and publish the results in several prestigious media outlets such as EE Times.

An Insight Award will be presented to the most innovative device in each of these categories:

• Process Technology
• Mobile Processor
• Non-volatile Memory
• DRAM

Mobile processor is a brand-new award. Our technology “academy” will compare the field according to such key metrics as power consumption, package design, thermal design, and integration. The selection committee includes these industry luminaries:

• Ed Keyes, CTO of SI
• David Carey, President of Portelligent
• Patrick Mannion, Editorial Director of TechOnline

along with senior Semiconductor Insights analysts specializing in each category.

Our second new category is reserved not for an actual IC but for the Best Patent Coverage of a Technical Innovation.

For a list of previous winners, go to 2007 winners. The Insight Awards will help your product achieve the recognition it deserves. The Insight Award Team feels strongly that there are a number of important benefits:

• Opportunity to be showcased in an SI authored article published in a major electronics publication
• Technical documentation including summary of winning highlights, device description, 3rd party validation of technical claims, and an Insight Report
• Award presented during the AceAward gala dinner
• Press release announcing each winner
• Recognition on SI and EETimes/ACEAwards websites
• Two posters highlighting an innovative technology area of the device delivered to you

I think they left out the cool plexiglas sculpture (design still TBD) which should be reason enough to submit your product. Joking aside, it is a great opportunity to get objective third party validation for your technology. You get worldwide bragging rights for a full year, and it’s another way for the engineers and the rest of your product team to feel good about their accomplishment. Past recipients look on their awards with pride every day and are inspired to create the next big thing in tech.

If you are interested in nominating a device or have any other questions about this program, please contact program coordinator, Crystal Carty (crystallc@semiconductor.com) at SI.

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The reason that utilities prefer solar thermal today is simple. Power engineers have a deep appreciation for rotating mass. Think about it. Every major power plant in the world uses its preferred source of energy to spin a turbine that’s attached to an electric generator. Hydro has it’s channeled waterfall. More commonly, heat generated by uranium, coal or natural gas turns water into steam that drives turbine blades. Solar thermal just uses the sun as the heat source. Electricity comes from a rotating machine. In fact, the one great proven renewable energy source installed on any significant scale is an icon of the turbine, obvious to just about anyone. I’m talking about the wind mill.  In fact images of wind power farms have come to represent much more than just the simple turbine. They are the preferred clip art, photo, or what-have-you for the much broader field of renewable energy.

All those big rotating machines are pretty good at storing energy too. have you ever thought about how long it takes a 100MW generating unit to stop spinning after you shut it down?

But what was the point of this again? Right. Solar power is a great technology that’s actually starting to be installed in significant quantities. It just so happens that for power plant installations, the preferred form is concentrators that focus the sun to heat water or another liquid. Various mechanisms use that heat energy to eventually spin a turbine driving a very traditional electric generator. On the other side of the solar power industry, there are the photovoltaics, known to clean tech hipsters as “PV.” If you haven’t heard, these are the “solar cell” devices that have been around for 170 years or so. They use a semiconductor material to convert photons from the sun directly into electricity. Before those electrons get onto the power grid, though, they need to jump through some hoops. Due to that grand old man of electric power generation, the rotating generator, electric utility grids the world over depend on alternating current or AC. Unfortunately (or fortunately if you are a supplier of power electronics IC’s) the PV panel produces a direct current or DC supply of power. PV panels require  a device known as an inverter to create grid-friendly AC from the DC supplied by the panel.

Electrical power utilities even store energy in rotating mass. “Spinning reserves” are used on peaking units used to quickly supply power when required. Storing energy in flywheels also allows some electricity generated slightly before peak times to be shifted out toward periods of peak demand. The maximum PV production usually coincides very well with peak demand, so this “load-shifting” is better suited to traditional coal-fired base load power plants since friction in traditional flywheel systems kills the momentum relatively quickly. For PV, the trick is obviously to store energy until after the sun goes down which is much longer than the typical big wheel can keep on spinnin’. But advanced flywheel research might change that. It actually sounds more exotic than the photovoltaics themselves.

It was a bit surprising to hear that California (or maybe the US in general) is not doing that much on the solar thermal front. As Rick Merritt reported in EETimes, Sue Kateley, executive director of the California Solar Energy Industries Association, was disappointed in the gap that had developed between California and places like Germany and Korea.

Solar power is a great source of renewable energy but an even better source of catchy headlines. In Days getting sunnier for solar in Silicon Valley, Sheila Riley reported on some more optimistic views of the industry in California. Rick and Sheila’s articles are definitely worth a read.

But the most natural way to store energy in a solar thermal system is just to keep the heat on tap until you need it. This “load-shifting” was one of many things George Leopold discussed in another recent EETimes article. Thermal storage is just one more reason to take a serious look at solar thermal for large power plants.

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For years the question, “How much is enough?” has been debated regarding NAND flash endurance. How many write cycles do you really need over the lifetime of a camera card or memory stick? How long do you need your portable data to stay intact?

SI’s senior memory analyst, Young Choi, attended the recent Flash Memory Summit in Santa Clara to hear what the vendors are saying about solid-state drives, or SSD’s. As NAND flash prepares to reach out and grab a chunk of the hard disk drive market, it will face even more scrutiny as we will all demand more endurance from the SSD’s that are just beginning to show up in select computers. As Young noted, “The overall impression is that the market is still in its infancy and it will take quite a while before enterprises and consumers adopt systems with SSDs.” And that was certainly the view of Fujitsu who cautiously observed, “the market and consumer are not happy about SSD overall.”

Participants were focused on three areas – performance, endurance and price. Many experts are calling for standardization of SSD performance metrics to eliminate the current state of confusion over SSD performance metrics. That would help avoid the “benchmarketing” we are often forced to suffer in this industry.

When I mentioned the NAND flash endurance debates of the past, I was alluding to the MLC versus SLC wars that have been waged over the years (often with Toshiba and Samsung as the respective combatants). The key information returned from the Summit was based on a usage model of 20GB per day for the typical consumer. This means that MLC NAND flash could provide sufficient lifetimes for consumer SSD products.

Several summit participants tried to predict the future of the SSD market by comparing it to the HDD market of long ago. Expect some major rounds of consolidation considering that there are more than 70 SSD manufacturers today.

But it seems like there is more driving SSD technology than simple bits and drive endurance. There is a shade of green overtaking the SSD conversation. Yes, saving energy and “going green” is a big part of the talk about SSD’s. At the Summit, the local California utility, PG&E, promoted the need to reduce energy demands through technological innovation. Their example was the power consumed by large data centers which can be reduced by transitioning to SSD.

Young mentioned that Intel will have some interesting things to discuss at the Intel Developer Forum August 19 through 21. Intel may concentrate on the controller for SSD, and this may actually be the key component to making NAND work in the SSD. The way operating systems use the hard disk is really tough on flash. For robust SSD’s in our future laptops, we will be relying on Intel and others to implement intelligent control and management of which physical memory locations are used to even out the wear over the whole flash chip over the life of the product. SanDisk has proposed their own version that they are calling LDE or Long Term Data Endurance.

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David Manners recently reported in Electronics Weekly that the semiconductor materials market will grow at double the rate of the chip industry. The actual numbers quoted from the SIA and SEMI respectively shake out as 4% for semiconductors and 9% for materials. It all sounds like solid growth - right?

Or does it? I fear that some solid-sounding numbers might be exploited to make things sound good when we might be headed for more trouble down the road. Where will the increase in tools and materials spending lead? Manners wisely attributed the more than double growth rate for materials to the combination of a rise in unit IC shipments coupled with a “steep decline in ASP…besetting the chip industry.”

Maybe I need to sign up for that remedial MBA program because I just don’t get it. What’s going to happen if the fabs’ spending rate on materials is increasing more than twice as fast as the revenues they get from the chips they manufacture?

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After my longest absence since starting SemiSerious, I thought it was about time to get posting again. For the handful of people actually reading this blog, I feel terrible about not keeping it going through the early summer. I hope to ramp up again in August with weekly posts appearing regularly by the time September rolls around.

Unfortunately, I have nothing semiconductor-related to post today. Instead, I thought I would just give an update on where I’ve been. My father passed away in June. After travelling back to Saskatchewan with my wife and two daughters for the funeral and other things, we took an extended family vacation. It just seemed like the right time for the kids to be with their maternal grandparents.

Now that I think of it, maybe a post about Dad is connected to semiconductors. I guess you could say he was there on the ground as consumer products transitioned to solid-state technology. Around the time I was born in the mid-sixties, my father was off work from the seed cleaning plant because of a workplace injury. He decided to use his unproductive time to enroll in a home self-study course in electronics - radio and television technology and repair. That led to a moonlighting business fixing TV’s (in our basement), then to a job at the local electronic parts distibutor, and eventually to his owning and operating that same parts business.

It was watching Dad in the shop that ignited my own interest in electronics. He always enjoyed having his kids around, so there were lots of opporunities to see him working. Dad taught me the resistor color code and Ohm’s Law.

In a lot of ways, it was difficult for Dad to watch the industry migrate from vacuum tubes to semiconductors. He was fascinated by the transistor and the IC, but the ever-decreasing cost of electronic products unsettled him. Cheaper TV’s meant fewer would ever be repaired. But it was not just about the loss of business for himself and his colleagues. It meant that more things were just thrown away and piled up in landfills.

My Dad was born in Southern Saskatchewan to immigrant parents (first generation North Dakotans) and spoke only Norwegian until picking up English at school where he completed the eigth grade. He was 83.

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OmniVision made the first announcement of a backside illuminated CMOS image sensor intended for the mass market two weeks ago. It seems their lead (at least in the PR world) did not last long as Sony made a similar claim this week. Gizmodo has front-side versus backside captured images along with a neat animated graphic comparing the two sensor structures.

As one news site pointed out, Sony is the “800 pound gorilla” in the image sensor business, so their announcement adds credence to the BSI concept. So there are now two manufacturers claiming to have developed a backside technology. And these are not just middling players. OmniVision and Sony are both “number ones.” OmniVision took over the lead in CMOS image sensors from Micron (now Aptina) last year while Sony is the world’s largest supplier of image sensors when you factor in both CIS and CCD.

Another news article from the past week reminds us that backside illumination is not a new concept in imagers built for scientific applications. NASA’s Mars Reconnaissance Orbiter is presently capturing digital images with an e2V CCD system. The probe’s High Resolution Imaging Science Experiment (HiRISE) instrument employs image sensors from the British company.

But the OmniVision and Sony sensors will be built for consumer applications. I’m guessing we might not see too many of these on the market for at least a year. Beyond that, though, it might be only a matter of another couple of years before the majority of imagers shipped “swap ends” for getting the light into the photodiodes.

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Last week, I posted a long, wordy (your own description might not be so flattering) article about OmniVision’s OmniBSI announcement. To sum up, OmniVision appears to be first out of the gate with a backside illuminated CMOS image sensor for the mass market. Despite the length of last week’s post, I left out an important detail that every other blog or news source - regardless of credibility - mentioned. As OmniVision’s foundry partner, TSMC is obviously a key player in bringing this new technology to production.

I apologize for omitting TSMC from the discussion. Although I don’t have any details on the working relationship or particulars of the processing TSMC might be applying to the OmniBSI products, the fab is certainly a central component in this process.

Image sensor guru Eric Fossum posted some insightful comments in the dpreview forum. (For more image sensor news go to Image Sensors World where I was pointed to this particular forum post.)In Eric’s words, “consider this announcement REAL and NEAR FUTURE.” That is an even stronger endorsement of his other description of “a major achivement by TSMC.”

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