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About SI
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Gate Dielectric Composition Analysis of
Leading Edge 65nm Logic Processes
High resolution lattice fringe TEM image of the gate dielectric indicates a dark layer suggesting a nitridation process was used. Full analysis with TEM-EELS reveals the complete compositional details of the dielectric. |
Special Edition Publication
"Challenges of 65nm Process"
Get a free copy of our special edition publication, "Challenges of 65nm Process" — an illustrated examination of five 65nm devices from Intel, Xilinx, Texas Instruments, and AMD.
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Detailed compositional analysis of gate dielectrics used in production IC's provides previously unavailable insights into this critical area of semiconductor technology. Our comparison report marks the first time ever that High Resolution TEM imaging and EELS materials analysis have been used to study one of the most challenging steps in semiconductor manufacturing.
In conjunction with analyst opinion about the state-of-the-art and future technology directions for gate dielectrics, our report analyzes and compares these specific processes:
- AMD HP 65nm SOI
- Intel HP 65nm
- Texas Instruments LSTP 65nm
- Xilinx UMC HP 65nm
Specific report details include the following:
- TEM analysis of the gate stack
- HRTEM lattice fringe imaging of the dielectric
- EELS profile for Si, O and N through the dielectric
- Absolute values and relative percentage compositions of Si, O, and N at key locations
- Gate dielectric thickness
Request more information about this report, including sample images, table of contents, and price by completing the form below.
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