Resources Reports Database Insights Newsletters Whitepapers Video Teardowns			Strained silicon: What does Intel know that IBM doesn't and vice versa? Interested in strained silicon? Our Strained Silicon report will provide you with the technical, market, and patent knowledge you need to know. Extending Moore's Law Depending on the chip maker, strained silicon promises a 20 to 35% boost in processor performance with an associated reduction in power consumption — in effect extending Moore's Law. As a result, strained silicon goes to the competitive core of the x86 processor market and is at the heart of the longstanding rivalry between Intel and IBM. The concept of strained silicon is not new and has been around for thirty years. However, it has recently moved to the forefront with intensified competition and the exhaustion of traditional methods of increasing transistor performance. Intel remains very guarded about its approach; however, most companies using strained silicon grow a thin layer of active silicon on top of a thicker layer of SiGe. Intel vs. IBM Intel will be the first to market with the Prescott — a Pentium 4 processor to be introduced in the second half of 2003 and operating at more than 3GHz. Intel's announcement to incorporate strained silicon at the 90nm node came as an industry surprise and a departure from Intel's normal late adopter approach. In contrast, IBM has announced its intention not to bring strained silicon to market until 2005 when it reaches the 65 nm node, choosing to focus on its SOI technology for now. SOI offers better performance OR lower power consumption, not both as is promised with strained silicon. As well, AMD is following the SOI path with its Hammer processors. Intel has announced a 10-20% performance improvement with only a 2% increase in cost. As well, Intel has indicated that it has figured out a way to achieve an acceptable balance between the NMOS and PMOS portions of its CMOS circuits. By contrast, IBM has announced a 10% cost premium delivering a 35% performance boost and that much work remains to balance the mobility enhancement in the NMOS and PMOS portions of a CMOS device. A closer examination of strained silicon Semiconductor Insights is planning a new report on the engineering of silicon-based materials for high performance devices. The report includes a look at the key players and how strained silicon fits into their technology roadmaps, an in-depth technical analysis of issues like performance, integration and production costs, as well as a look at the pros and cons of using strained silicon. The report will also include an examination of patents currently held by the key players. For More Information: Learn more about our Strained Silicon Report Contact: simonel@semiconductor.com        Quotable "It is pretty clear that Intel has made a major breakthrough here. It is amazing that they would use strained silicon at the 90nm node, and if the cost adder is only 2% then the process additions would need to be pretty trivial." Dan Hutcheson, President, VLSI Research About Strained Silicon Strained silicon takes advantage of the natural tendency for atoms inside compounds to align with one another. When silicon is deposited on top of a substrate with atoms spaced farther apart, the atoms in silicon stretch to line up with the atoms beneath, stretching -- or "straining" -- the silicon. In the strained silicon, electrons experience less resistance and flow up to 70 percent faster, which can lead to chips that are up to 35 percent faster -- without having to shrink the size of transistors. Above: Illustration of a structure utilizing strained silicon
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